Mitigando o impacto da comunicação no consumo de energia e área em chip pela utilização de uma infraestrutura de comunicação híbrida em sistemas multiprocessados

Abstract

The increasing integration of many processing elements inside the same die has been raising the need to create efficient communication infrastructures. Different structures have been exploited to interconnect those elements, such as NoCs, crossbars and buses, each one being commonly employed separately. However, current MPSoCs have faced severe design constraints that must balance area and communication efficiency. The contribution of this work is the proposal of MPSoC-HSC (Multiprocessor System on Chip with Hybrid Communication Structure) which merges the concepts of the three analyzed communication infrastructures (Bus, NoC, Crossbar) in a single platform. The main contribution is the creation a communication infrastructure more efficient when selecting the best characteristics out of different communication structures. The infrastructure MPSoC-HSC when compared with is NoCs Hermes save area, power and energy in 49%. HSC in comparison with crossbar infrastructure save area in 29% and growth power and energy in 72%. The results of HSC related growth power and energy are explained the relation of size crossbar and their technical features, influence on area and impact on power result.