Projeto e análise de moduladores Sigma-delta em tempo contínuo em tecnologias CMOS

Abstract

This work presents the design of a continuous time sigma-delta modulator with a 0.2 MHz signal bandwidth and 78 dB signal-to-noise ratio (SNR), which are the specifications for the GSM standard. Three single-loop, single-bit, low-pass modulators are implemented, being one of second order and two of third order, where the one with higher order has a more aggressive noise transfer function. A stability analysis is performed together with the real modulators performance when compared with the ideal one. The stability analysis can be applied for continuous or discrete time modulators since control and filter theory are used. System level results show that the second and third order architectures have equivalents signal-to-noise ratios when stability is considered. Besides, several non-idealities are compared in order to verify the second order modulator robustness. Results from the electrical implementation show that the modulator achieves a superior signal-to-noise ratio than the counterparts due to other non-idealities present in CMOS circuits. Final results reveals a significant reduction in the modulator design and power consumption. Therefore, this work emphasizes that the designer should perform a thorough system analysis before implement the modulator resorting only in the ideal equation that predict the sigma-delta modulator performance in order to verify if a simple architecture could result in a similar performance than a more complex system.