Descrição em VHDL de um processador RISC-V RV32EC

Abstract

The design of processors has as its starting point its specifications, considering the application, the size and type of data to be processed, and the instruction set architecture (ISA) executed by the hardware. In many ISAs, licensing is not free, making it difficult for research for educational and academic purposes. In this work we use the base E and extensions C of ISA RISC-V, a free and open source ISA, in the design of a 32-bit processor described in VHDL. The synthesis and implementation of the design were performed in the Xilinx ISE Design Suite 14.7 software, on the Spartan-6 XC6LX16-CS324 FPGA, available on the Nexys 3 development board. Base E uses 32-bit integer data, with 16 general purpose registers, while extension C provides 16-bit compress instructions. Was studied the instructions to be implemented, identifying the units necessary for the development of a processor with two different core, a multicycle and a 5-stage pipeline. The multicycle core processor executes only C extension instructions, RVC, while the pipeline runs the complete set, RV32EC. The necessary components for the practical execution of the core were designed, being the program and data memory, and two I/O devices. Both designs were implemented in the FPGA with a minimum speed of 100 MHz. In the implementation of the multicycle it was clear the waste of using the C extension alone, since it gains space in software, not hardware. While in the pipeline is was noticed the effect of memory latency upon the core, which ended ignoring specifics paths of the hardware.