Desenvolvimento de estrutura de controle para paralelismo de inversores aplicados em fontes ininterruptas de energia

Abstract

This master's thesis proposes a control structure for inverters parallelism on uninterruptible power supply (UPS) modules with low line impedance characteristics. The structure is based on instantaneous current sharing (ICS), by exchanging information between modules through a communication bus. However, the system requires lower communication rates than others ICSs methods, and in addition, presents greater tolerance to output voltage measurement errors. In this system, one module act as a master, generating the synchronism of the voltage references, besides transmitting to the modules its output voltage measurement and LC filter inductor current. The slave modules, as well as the master, execute a voltage control loop and a current control loop, however, they use the master module measurement as a reference to generate errors coefficients that will be used to correct their own measurements. Using these coefficients, the relative measurement errors between the modules are eliminated. The coefficients are updated with each transmission of the master, whose transmission occurs at every 10 periods of voltage control loop sampling. In addition, the modules use a virtual impedance inserted in the circulating current, whose virtual impedance modifies the amplitude of the voltage reference of these, whenever there is difference between the currents of the slaves with respect to the master. This type of virtual impedance has the advantage that it does not affect the regulation of the output voltage. A system with two 2 kVA modules is designed and implemented. Simulation results are obtained with the detailed analysis of the structure. Finally, experimental results are obtained to validate the proposed structure.