Acoplamento e validação funcional do sistema reconfigurável DIM

Abstract

Reconfigurable architectures have been widely employed to speedup applications by exploiting instruction level parallelism, appearing as an alternative to replace the power-hungry circuits of superscalar processors. The DIM system is an example of a reconfigurable architecture. This system already shown significant speedups to execute embedded applications. However, the performance results have been gathered by using an instruction accurate description of the architecture. Aiming to gather more accurate performance results and data about power consumption of the DIM system, this work proposes the functional validation of the DIM architecture using an existing VHDL description. As a contribution, some applications were used to validate the existing hardware description. The validated VHDL description presents an overhead of 0.45% in the power consumption and of 0.25% in the area occeupied in comparison to the non-validated version.