Projeto de comparadores strongarm com calibração de offset

Abstract

Comparators are circuits that, given two signal inputs, return as a result a value referring to which of these signals has greater magnitude. This behavior makes the comparator a key component in the design of analog-to-digital converters (ADCs), as it can be understood as a circuit that takes analog inputs to a digital output. With the advancement of integrated circuit manufacturing technologies, as well as the increasing demand for mobile and IoT devices, it is increasingly necessary to reduce power consumption and the area required by components, without compromising their speed and accuracy characteristics. However, these operational characteristics are typically antagonistic, causing design choices made to improve one characteristic to have unintended consequences on another. For the comparator, reducing the area is directly related to reducing power consumption while increasing the error rate in comparison. Therefore, it is necessary to understand the interdependencies between each of the comparator’s operating parameters in order to ensure the optimal circuit design for the desired application. From this perspective, this work aims to relate the operating parameters of a StrongARM topology comparator as a function of a common variable and, based on this, propose a design methodology capable of meeting the specifications of the desired application by combining the sizing of the comparator with the design of an auxiliary circuit for offset compensation. As a result, it was possible to design a calibrated comparator with an estimated area 95 times smaller, and 55 times lower power dissipation, meeting a precision requirement three times higher than the original uncalibrated comparator designed.