Design of 12bits incremental sigma-delta adc using feedforward topology for slow signals applications

Abstract

This undergraduate thesis aims to present the design of a 12-bit Incremental Sigma-Delta Analog-to-Digital Converter using the FeedForward topology for slow signals applications. The demand for slow signals electronic systems has significantly increased, driven by applications such as mobile devices, wireless sensors, and battery-powered systems. Not only precision but also energy efficiency becomes a critical factor to be considered in integrated circuit design, especially in analog-to-digital converters. The division of tasks for the development of this work was organized into two main stages. The first stage involved the modulation of the Sigma-Delta modulator using Matlab-Simulink, which consists of creating ideal blocks using the Simulink library, following by adding nonidealities using sigmadelta toolbox, while an pararel script in Matlab is executed to determine the gain coeficients of the Modulator. This methodology allows to test different low-level topologies without projecting the circuit at transistors level, gaining time. At this stage, theoretical studies and analyses were conducted too for better decision making and subsequent implementation of the ADC. In the second stage, the design of the 12-bit ADC at transistor level in Cadence - Virtuoso was carried out, integrating it with the Matlab model from stage 1. It involved the design of the OTA, Comparator, DAC and Logic Control circuit. At the end of this work, the objective is to obtain a 12-bit ADC, capable of operating efficiently in terms of power consumption (in the range of micro-Watts) and with an INL (Integral Non-Linearity) lower than 2 LSB (Least Significant Bit). The development of this ADC can contribute to the advancement of slow signals technologies, paving the way for the implementation of more efficient and sustainable electronic systems.