Implementação de arquiteturas de pilha UDP/IP em hardware reconfigurável baseado no desempenho de vazão, latência e taxa de perda de quadros

Abstract

This work presents the implementation of three architectures of UDP/IP network stack in reconfigurable hardware. Also, presents the development of a Tester based on the RFC 2544 methodology and implemented it in FPGA. This Tester was used to obtain the throughput, latency and frame loss rate results. The performance of the project shows, in average, throughput results 89% better in comparison with a network stack implemented in software (PC) and running over a general purpose microprocessor, for frames with 64 bytes. Regarding latency, the project is 389 times lower for frames with 64 bytes and 13 times lower for frames with 1518 bytes, than the PC. On behalf of frame loss rate, the project doesn t loss frames for any frame sizes used during the tests, while the PC has presented a frame loss of almost 98% for frames with 64 bytes.