Exploração de operadores aritméticos na transformada rápida de Fourier

Abstract

The power consumption reduction in the fast Fourier transform (FFT) is important because applications in battery-powered embedded systems grows daily. Thus this work focuses on the application of techniques to reduce power in specific projects of FFT algorithms. The goal is to achieve an architectural exploration in the FFT core, the decimation in time butterfly radix-2 and the efficient implementation of arithmetic operators in the internal structure of this butterfly. The techniques applied to the butterfly are aimed at reducing power consumption through architectural exploration and data encryption. Five different butterfly topologies are shown, one of those, proposed in this work uses three real multipliers, and is based on the previous storage of the product of real and imaginary values of the twiddle factors. The advantage of this topology is the possibility of using 4:2 adder compressors, which performs the sum of four operands simultaneously with reduced critical path. These adder compressors have XOR gates in the critical path, is proposed in this paper a new XOR gate circuit, which is based on the use of pass transistors logic. This new XOR gate circuit has been applied to adder compressors 3:2 and 4:2, which are applied to adders blocks of the butterflies. Digital circuits have been developed in hardware description language and some in the electrical schematic level. Results of area, power consumption and cell count in the logic synthesis in 180nm at 100MHz and 20MHz with switching activity analysis for 10,000 random input vectors were obtained for this work. The electrical level simulations in an environment of mixed digital and analog signals were also performed to the evaluation of the compressors with new topology of XOR gate. Analyses show that 3:2 adder compressor has lower power consumption using the new XOR gate circuit. However, the same conclusion was not achieve in relation to the 4:2 adder compressor which has a lower power consumption using the CMOS XOR gate. Butterfly structures evaluated uses a significant amount of arithmetic operators in their internal structures, so was used different design strategies for implementation. Initially was used the arithmetic operators of automatic synthesis tool (Cadence). After, used dedicated arithmetic operators (adder compressors with the new XOR gate circuit, RNS adders and array multipliers). The results show that butterflies have lower power consumption with the use of adder compressors in their internal structures.