Nova metodologia para a estimativa de capacitância e consumo de potência de portas lógicas complexas CMOS no nível lógico

Abstract

This dissertation presents a methodology of capacitance estimation and power consumption in CMOS circuits combinational constituted basically of complex logic gates at logic level. The main objective in the development of this method is to provide a fast estimate of the power consumption of circuits at the logical design gates. Of this form, the considered method allows to the application of techniques to the reduction of power consumption or the alteration of the design before being prototyped. The consumed dynamic power in complex logic gates depends on the following factors: switching activity of each circuit node, voltage of supplies, parasite capacitance and clock frequency. With the exception of the parasite capacitance, all other parameters are easily determined. The analysis proposed in this dissertation, treats estimative of the dynamic power consumption of complex logic gates, through the estimate of the parasite capacitance CMOS devices. The model considered here concentrates all internal capacitances on the external gate nodes depending on the combinations of the input signals. The resulting capacitance in an only external node of an input of the gate is resulted of the transitions of inputs of the too much nodes on the node that if wants to determine. The results obtained in this work, regarding the estimate of power consumption of the complex logic gates, had been considered satisfactory, once they had presented a maximum error of 10% when compared with to the electric simulation result preformed with ELDO. Moreover, the method supplies significant reduction in the simulation time of the circuits, being able esteem the power consumption of a circuit up to 200 times faster than gotten to the simulated electric level with ELDO tool.