Prototipação e análise de circuitos mutiplicadores array de baixo consumo

Abstract

This work presents the prototyping and analysis of new multiplier architectures under the physical level of abstraction. Circuits recently presented in the academic community are analyzed and compared against the state of the art. The new architectures operate on signed multiplication and maintain the pure form of an array multiplier. These architectures are extended for radix-2m encoding, where m is the number of the bits, which leads to a reduction of the number of partial lines. The proposed approach significantly improves the state of the art, enabling gains in performance and power consumption. Such aspects are attractive for the implementations of the new multipliers in the physical level. For the most of the systems, functionality tests are used in order to verify if a circuit is functionally equivalent to a given specification. These types of tests have to be the first part of the development of the circuit. Thus, we have developed in this work a flow of the circuit analysis. This flow covers since the functional tests, passing through the stages of physical synthesis in transistors level and FPGA, until the prototyping in Silicon of the architectures. In this work, we have used the same test vectors in all the stages of the project which involves, since the verification of the logical functionality until the extraction of the power consumption in physical level.