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Implementação e avaliação de desempenho de um código corretor de erros multi-bit em memórias SRAM
(Universidade Federal de Santa Maria, 2022-02-18)
The present work presents the performance analysis and the implementing of an ECC
capable of correcting 4 bit-flip generated by a single MBU. For this, its HDL code was developed
and generated the test vectors for ...