Projeto de um conversor A/D sar com compartilhamento de carga: sintese lógica do controle e projeto elétrico do DAC e comparador

Abstract

The paper presents the design of a successive-approximation-register (SAR) analogto- digital converter (ADC). The most usual construction of the SAR ADC requires a logic control circuit, a digital-to-analog converter (DAC), and a comparator circuit. The logic control block is described in Very High Speed Integrated Circuits Hardware Description Language (VHDL) and synthesized using the Cadence Software Register Transfer Level Compiler (RTL)® tool. Regarding the DAC block, the charge-sharing (CS) architecture was chosen since it presents a lower power consumption when compared to the charge-redistribution (CR) architecture. Comparator design techniques are employed to mitigate comparison delays, and therefore reduce ADC conversion time. The 6-bits SAR ADC CS requires a voltage supply of 1.8 V and converts differential input signals, which ranges from 0 V to 1.8 V. The converter is designed in Complementary Metal- Oxide-Silicon (CMOS) technology using the TSMC180 (CMOS 0.18um) manufacturing process, using the Process Design Kit (PDK) - MIXED SIGNAL RF GENERAL PURPOSE II. The implemented ADC achieves a effective number of bits (ENOB) equal to 5.2 bit for a 12.5 MSa/s conversion frequency. The maximum DNL error registered is +0.53 LSB, with INL errors within the range of 0.4 LSB. The power consumed per sampling is around 292 W, with the figure of merit equal to 645.26 fJ/convertion.