Uma proposta de arquitetura de pilha de comunicação em rede com um número reduzido de camadas

Abstract

This work presents a network stack architecture proposal with a reduced number of layers. The reduction in number of layers aim to provided a simpler and efficient communication method to embedded systems by allowing the microprocessor, where usually application is implemented, run just application code and not running code related to network communication. The architetucture was implemented on and FPGA board and show, in average, throughput results around 27 times better in comparision with a network stack implemented in software and running over an embedded microprocessor.