Exploração de comunicação fim-a-fim assíncrona através de uma NoC síncrona

Abstract

Systems on-Chip (SoC) with a large number of cores adopt Networks on-chip (NoC) as the communication infrastructure due to its scalability. The complexity to distribute a skew-free synchronous clock signal over the entire chip increases in current fabrication technologies due to the process variability. The transistors energy consumption hasn’t remained proportional to the increase in integration density, breaking the Dennard’s scaling, as a consequence, today it is not possible to keep every core in full operation whitout breaking the limits of energy consumption, this phenomenon is called as Dark Silicon. Thus, designers may choose among asynchronous and Globally Asynchronous, Locally Synchronous (GALS) NoCs. This work proposes an intermediate solution. Each Intellectual Property (IP) core may have its clock domain, and the NoC supports both synchronous and asynchronous communication. The asynchronous communication is implemented in the NoC using a technique called bypass over internal buffers. During runtime each router in the path between the transmitter and the receiver has its internal buffers bypassed, creating a direct connection between each IP and allowing them to communicate without the NoC clock domain interference, this is called end-to-end communication. The asynchronous communication reduces the switching activity inside the NoC because router buffers are bypassed. The communication between IPs and NoC requires some synchronization technique that must be applied to contain the metastability in data transmission between clock domains. However the most traditional technique to make the synchronization between NoC and IP is a bisynchronous FIFO which proved to be unsatisfactory due to high latency penalty when associated to the asynchronous communication protocol. To work around this problem the bisynchronous FIFO has been changed by the border synchronization, which makes individual sinchronizations when a control signal is crossing to another clock domain. This technique associated with an asynchronous circular FIFO proved satisfactory in terms of energy reduction (up to 52%) under latency (16% to 30%) and area (21%) overhead.