Implementação e avaliação de desempenho de um código corretor de erros multi-bit em memórias SRAM

Abstract

The present work presents the performance analysis and the implementing of an ECC capable of correcting 4 bit-flip generated by a single MBU. For this, its HDL code was developed and generated the test vectors for validation of its operation and then implementation in FPGA and ASIC. For its implementation in FPGA, was used Xilinx’s Spartan 3, Spartan 6 and Artix 7 families because they have different design technologies, allowing a comparison between them. For implementation in ASIC, the logic synthesis was performed using XFab’s XH018 design kit and its modified radiation tolerant (RH) version of SMDH. With them, 3 syntheses were made, one with the highest frequency without modifications (XH018 Fast), one with the highest frequency radiation tolerant (XH018 RH) and the last without modification at the same frequency as the modified version (XH018 Normal), then it was performed area, power and frequency analysis between them and the FPGAs, concluding that if you are not going to make circuits using radiation tolerant transistors, it’s possible to use Artix 7 because it has a 17 % lower frequency.