Design space exploration of hybrid topologies and DVFS in on-chip communication networks

Abstract

Multi-Processor Systems-on-Chip (MPSoCs) have been established as the standard platform for high-performance applications in the semiconductor industry. With an increasing number of Processing Elements (PEs) within a die, scalability is one of the foremost concerns. Networks-on-Chip (NoCs) have been proposed as a way of mitigating this issue, as an alternative for the well-known design techniques, using Busses and Crossbars, for interconnecting PEs. Despite providing the necessary means for scalable communication, NoCs are still associated to great power and on-chip area costs. Recent research efforts have demonstrated the use of Dynamic Voltage and Frequency Scaling (DVFS) as a promising way of dealing with these challenges. This work aims to make the following contributions to the study of on-chip interconnection networks: Explore the use of hybrid topologies, with Busses, Crossbars and NoCs in the same network, as a way of reducing power and area costs in interconnection networks at design-time; and Propose a DVFS implementation for further power savings at run-time. Demonstrating the effectiveness of the proposal, in the experiments performed, a difference of up to 22% in power and 42% in area can be found between a hybrid topology and a NoC with the same number of PEs. With DVFS, simulations with popular video encoding applications show a power consumption gains of up to 70%, with no signifcant throughput losses in the majority of simulated scenarios.