Projeto e análise de um PLL de terceira ordem em tecnologia CMOS

Abstract

In this work, a Phase-Locked Loop (PLL) circuit is developed for frequency synthesis. The chosen topology is third-order, and a current mismatch compensation technique is employed in the Charge Pump. The electrical design, developed in CMOS technology, considered specifications for area and power consumption and was adjusted to withstand variations in temperature, supply voltage, and processes. The designed PLL increases a frequency from 20MHz to 240MHz, achieving an RMS jitter of 82 picoseconds RMS, with a power consumption of 115μW and an estimated area of 0.0026mm2.